An IIL logic circuit which requires no separation for each element has recently been used to enhance the integration density of an integrated circuit. Japanese Patent Disclosure No. 49-24329 discloses a semiconductor memory device having a plurality of flip-flop type memory cells constructed with the use of an IIL logic circuit of this type and arranged in a matrix array. In this type of semiconductor memory device, read and write operations are selectively effected through the same address transistor with respect to each memory cell. In this case, a data output signal read out of the memory cell through the address transistor does not have a sufficiently great logic amplitude and in order to positively detect the data output signal a data detection circuit of a complicated structure is needed, making the occupation area of the memory device greater as a whole.
It is accordingly an object of this invention to provide a semiconductor memory device which reads out memory data as a logic signal having a sufficiently great logic amplitude and positively processes data without using a complicated data detection circuit.